This invention relates to a latch circuit suitable for semi-custom integration, more particularly to a latch circuit with complementary output signals in which initializing signals such as set and reset signals have priority over latch signals.
Semi-custom integrations are created by interconnecting a set of standardized circuits on a semiconductor chip supplied by a manufacturer to obtain a device with desired functions. Use of semi-custom integrated circuits, typified by so-called gate arrays and application-specific integrated circuits, has become widespread. The standardized circuits employed range from simple logic gates to large macrocells. The standardized latch circuits of the present invention are intermediate in this range.
In designing a semi-custom integrated circuit, the user relies on timing parameters supplied by the manufacturer. In the case of a latch circuit, these timing parameters include, for example, setup time, hold time, input-to-output propagation delay in the unloaded state, and dependency coefficients indicating how the propagation delay increases with the size of the load. It is desirable that these parameters be constant and not vary according to the input and output connections of the circuit in question.
In the case of a circuit with two outputs it is undesirable for the timing parameters of one output to be influenced by the load coupled to the other output. This consideration applies in particular to a standardized latch circuit with two complementary outputs. A latch circuit in which the non-inverting output signal is branched to an inverter that generates the inverting output signal is unsuitable for semi-custom integration, because the propagation delay of the inverting output signal depends strongly on the load of the non-inverting output signal. The same problem occurs in latch circuits that use the inverting or non-inverting output signal as a feedback signal.
One way to avoid such unwanted interactions between the outputs of a latch circuit would be to add more inverters, so that each output signal is driven by an inverter which in turn is driven by an internal signal. Increasing the number of inverters, however, adds to the overall propagation delay, making the resulting latch circuit unfit for high-speed operation.